| [1] LI Yan-wei. Design of Adaptive Equalizerand VCO in High--speed SERDES [D].Jiangsu：SoutheastUniversity, 2015:1. [2] Gong Y,Cowan C F N.An LMS style variabletap-length algorithm for structure adaptation[J].IEEE Transactions on SignalProcessing, 2005, 53(7):2400-2407. [3] 陈福民．自适应信号处理[M]．西安：电子科技大学出版社，2002：20—30页. [4] Nicolle B，Tatinian W，MayolJ J，et a1．Top-down PLL design methodology combingblock diagram，behavioral，and transistor-level simulators[C]．IEEE RFIC Symposium，Honolulu，Hawaii，2007．475-478. [5] LIAO C F, LIU S I. A 40Gb/sCMOS serial-link receiver with adaptive equalization and CDR[C]. IEEEInternational Solid-State Circuits Conference(ISSCC), 2008: 100-598. [6] HSIEH C L, LIU S I. A 40Gb/s adaptive receiver with linear equalizerand merged DFE/CDR[C]. IEEE Symposium on VLSI Circuits (VLSIC), 2011:208-209. [7] 张会，刘伯栋．基于眼图分析的数字通信干扰效果方法研究[J]．舰船电子工程，2011，31(2)：73-76． [8] CHOI J S, HWANG M S, JEONG DK. A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with jointadaptation method of low-frequency gain and high-frequency boosting[C]. IEEESymposium on VLSI Circuits (VLSIC), 2003: 103-106. [9] CHOI J S, HWANG M S, JEONG DK. A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer usingenhanced low-frequency gain control method[J]. IEEE Journal of Solid-StateCircuits, 2004,39(3): 419-425. | 
